1. Field of the Invention
The present invention relates to an analog/digital converter, and, more particularly, to a monolithic analog to digital converter (hereinafter called "A/D converter") which is fabricated by the MOS technology.
2. Description of the Related Art
Conventionally, a successive approximation type A/D converter is known as an A/D converter fabricated by the MOS technology.
FIG. 1 is a circuit exemplifying this conventional successive approximation type A/D converter. As shown in FIG. 1, the conventional successive approximation type A/D converter includes a resistor-string type digital to analog converter (D/A converter) 1. This D/A converter 1 has a plurality of resistors 5 (resistance R) connected in series, and a plurality of switches 6 each of which selectively acquires the voltage across the associated resistor 5. The A/D converter equipped with this D/A converter 1 further has a comparator 2, a successive approximation register 3 and a switch controller 4. The comparator 2 sequentially compares an analog signal input to an analog input terminal 7 and supplied to the comparator 2 via a switch 8, with the output of the D/A converter 1, input via a switch 9. The successive approximation register 3 holds the output of the comparator 2. The switch controller 4 controls the individual switches of the D/A converter 1 based on the output of the successive approximation register 3.
While this conventional A/D converter can advantageously permit an easy simple increase in the number of bits, the increase in the number of bits inevitably increases the chip area. More specifically, this conventional A/D converter requires 2.sup.N resistors 5 and (2.sup.N+1 -2) switches 6 in the case of N bits, and an increase in the number of bits significantly increase the chip area.
In this respect, therefore, there is a demand for an A/D converter, which has the advantage and feature of the resistor-string system and has a circuit structure to suppress an increase in the chip area.
FIG. 2 is a circuit diagram showing another conventional A/D converter designed to suppress an increase in the chip area. As shown in FIG. 2, this A/D converter includes an M-bit D/A converter 11 having a string of unit resistors 25 of a resistance R and a plurality of switches (not shown in FIG. 2) each of which selectively acquires the voltage across the associated resistor, and an N-bit D/A converter 15 having series-connected resistors 26 of a resistance R/2.sup.N. A comparator 12 has a differential amplifier 22, a capacitor 20 connected between one input terminal of the comparator 12 and one input terminal of the differential amplifier 22, and a switch 21 connected between a pair of input terminals of the differential amplifier 22. The output of this comparator 12 is input to a successive approximation register 13. The output of the successive approximation register 13 is input to a first switch controller 14 and a second switch controller 16. The first switch controller 14 controls the switches of the D/A converter 11 and leads the output of the D/A converter 11 via an output line 23 to the aforementioned one input terminal of the comparator 12. A switch 19 is provided to this output line 23. The second switch controller 16 controls the switches of the D/A converter 15 and leads the output of the D/A converter 15 via an output line 24 to the other input terminal of the comparator 12. An analog input terminal 17 is connected via a switch 18 to the aforementioned one input terminal of the comparator 12.
This A/D converter of n (=M+N) bits comprises the resistors and switches, the number of which is about 1/2.sup.N compared to that of the simple resistor-string type n-bit A/D converter shown in FIG. 1.
FIG. 3 is a detailed configuration of the second D/A converter 15 shown in FIG. 2. As shown in FIG. 3, each resistor 26 of the second D/A converter 15 is constituted of 2.sup.N unit resistors 25 of a resistance R connected in parallel.
To improve the precision of the above conventional A/D converter, the resolution of the N-bit second D/A converter 15 should be increased. Since the second D/A converter 15 has 2.sup.N unit resistors 25 of a resistance R connected in parallel, the chip area inevitably increases as N increases.